New 10 February 2004.

Improvements in Digital Computers

Patent Number: WO8809007
Publication date: 1988-11-17
Inventors: Richard Miller, James Westwood
Applicant: Cambridge Computer Limited

Abstract

WO 88/09007	                                      PCT/GB88/00360


                 IMPROVEMENTS IN DIGITAL COMPUTERS
                 ---------------------------------
     The present invention relates to digital computers,
particularly so-called personal or home computers designed for
minimum manufacturing costs. The essential elements of such a
computer are the CPU itself, RAM, ROM and an assemblage of logic
which provides the means of connecting together and passing control
signals between the CPU, RAM, ROM and various peripheral devices
such as a display device and a keyboard. It is well known to
integrate a large proportion of the logic in a gate array (there are
various other names), which is a large IC containing some thousands
of gates which are interconnected to provide the required assemblage
of gates, flip-flops, registers, counters and so on. By use of such
an array it is possible to construct a computer consisting very
largely of just four chips - CPU, RAM, ROM and gate array.

     One commercially available gate array has approximately 3500
gates and 100 pins. Such an array is capable of handling fairly
sophisticated peripheral facilities for a home computer but the
problem of pin-limitation becomes apparent. The object of the.
present invention is to provide a computer which is so constructed
that certain peripherals can be served without the dedication of
specialised ports thereto.

     The digital computer according to the invention comprises, a
CPU, RAM, ROM and an assemblage of logic providing ports for a
plurality of peripheral devices and is characterised in that the
logic is arranged, in serving at least one peripheral device, to
stop the CPU clock for an interval sufficient to allow settled
drive or sense conditions for that peripheral device to be
established.

     The CPU must be such that it does not lose the data in its
internal registers when the clock is stopped. This is true of a
CMOS CPU. An advantage of the invention, as applied to a portable,
battery-driven computer, is that the power taken by a CMOS CPU
while its clock is stopped becomes negligible.

     Two particular embodiments of this invention are present in the
computer to be described below. In one embodiment a keyboard
matrix is connected directly across ports of the CPU but with the
interposition of buffer resistors which ensure that held keys will
not load any part sufficiently to impair running of the computer.
However, when the CPU is performing a key-scan routine, the clock is
stopped long enough each time before a keyboard output line is
sensed for its level to settle high or low, depending upon whether
a corresponding key-switch is closed or not.

     It will be appreciated that the clock oscillator itself is not
stopped. The CPU clock signal is stopped in the sense that it is
prevented from reaching the CPU. The clock signal will continue to
be used by the logic array.

     In the other embodiment of the invention, the CPU and logic
are enabled to act as an EPROM programmer by writing to an EPROM in
normal address space but using lengthened write pulses achieved by
stopping the CPU clock.

     The invention will be described in more detail, by way of
example, with reference to the accompanying drawings, in which:


     Fig. 1 is a schematic diagram showing the architecture of a
computer embodying the invention,


     Fig. 2 shows some parts of a logic array, and


     Fig. 3 is a diagram of the keyboard.

     The computer shown in Fig. 1 comprises a CMOS Z80 8-bit CPU 10
connected to a logic array 11 by an 8-bit data bus D0-D7, a 16-bit
address bus A0 to A15 and a control bus C containing the well known
read/write, interrupt and other control lines of a Z80 CPU.

     A keyboard 12 is connected across the address and data buses,
as will be described below. The logic array drives a display
device 13, such as a LCD display. The logic array also has
channels 14 communicating with other ports such as a serial port.

     The basic 64kbyte address space is treated as composed of four
16kbyte segments, which will be called segment 0 (0000H to 3FFFH) to
segment 3 (C000H to FFFFH). The logic array 11 includes four 8-bit
registers 15, any one of which at a time can drive an 8-bit address
extension bus B0 to B7. A14 and A15 are used to select between the
four registers. Bits B6 and B7 of the selected register select
between four slots 0 to 3. Bits B0 to B5 select between 64 pages in
the selected slot while A0 to A13 select addresses within the
selected page of the selected slot. The total address space
accordingly consists of 64 x 16k = 1 Mbyte per slot, 4Mbyte in all.

     The logic array 11 thus communicates with all memory devices by
way of a 20-bit address bus AA (comprising A0 to A13 plus B0 - B5),
an 8-bit data bus D'0 - D'7, a control bus MC and four chip-enable
lines CE0 to CE3 decoded in the logic array from B6 and B7 and
selecting the four memory slots respectively.

     The bottom slot, slot 0, is treated in two 512Kbyte halves
assigned to MOS ROM 16 (8 pages, 128kbyte) and to internal RAM 17 (2
pages, 32 kbyte). The other three slots are assigned to three plug-
in memory modules 18, 19 and 20 which may be RAM modules for memory
expansion or ROM modules for plug-in programs. The connector 21 for
the top slot, slot 3, is moreover equipped to apply a programming
voltage Vpp to enable an EPROM module 20 to be programed. By means
of the present invention it is possible to effect this programming
directly off the address and data buses extended to the module 20 via
the gate array 11 and connector 21.       Slot 3 normally operates
like slots 1 and 2, i.e. normal read and (if RAM is in the slot)
write operations may be effected. However a bit is used in the
logic array 11 as a flag to select between normal operation and
programming mode.    When this bit is set, the circuit described
below with reference to Fig. 2 is brought into action.    A separate
bit is set/reset to control the application of the programming
voltage Vpp.

     Features of the logic array 11 are shown in Fig. 2.  A
particular address range, namely the top slot, is dedicated to EPROM
programming, when the flag bit mentioned above is set. When the
CPU 10 wishes to program an EPROM byte, it establishes the required
address by way of the bus A0 to A15 and one of the registers 15 (B0
to B7) and the required data is put on to the data bus D0 to D7.
The logic array 11 includes a decoder 22 which detects any extended
write address in the programming range (B6 = B7 = 1) and issues a
signal PROGRAMA which stops the CPU clock PHI from passing to the
CPU, via a latch 26 and gate 28.  After a delay, introduced by delay
stage 23, of about 2  seconds (FRONT PORCH) a latch 27 is set, which
in turn will activate the appropriate control signals to the EPROM
(such as PGM  OE and CE, depending on the EPROM type).

     The delay stage 24, is programmable, to accept various EPROM
programming times.  After the delay 24, the latch 27 is reset, thus
releasing the EPROM from its programming mode.  A delay 23 (BACK
PORCH) lasts for about 2  seconds, after which the clock to the CPU
is started again.  Vpp is applied throughout this sequence of
operations.  The delay time of the delay 24 may be programmed to
allow the CPU to perform a program then verify cycle repeatedly in a
training stage during which the appropriate minimum delay for secure
programming of the EPROM is ascertained.

     It can thus be seen that the EPROM is programmed directly off
the address and data buses A, D'0 - D'7 rather than off a separate
register set up to buffer the input signals which have to be held
over a very large number of CPU clock cycles.

     Fig. 3 is a block diagram of the keyboard 12 which has eight
row conductors 1 to 8 and eight column conductors A to H.  A simple
key-switch (not shown) is provided at each of the sixty-four
intersections and a depressed key connects the corresponding row and
column conductors.  The column conductors A to H are connected via
diodes 30 and 2.2kohm resistors 31 to the address lines A8 to
A15 respectively.  The row conductors 1 to 8 are connected to +5V
via 100 kohm pull-up resistors 32 and to the data lines D0 to D7
respectively via 47 kohm resistors 33. Keyboard sensing is by the
well-known technique of sending a walking bit along the column
conductors A to H and detecting which row conductor is pulled low.
However the present invention makes it possible to do this with
direct connection across the address and data buses, as will now be
explained.

     The diodes 30 and resistors 31 ensure that the CPU can always
drive the address lines A8 to A15 as it wishes;  they are not so
loaded as to upset the drive thereof.  On the other hand the large
resistors 33 ensure that the data lines D0 to D7 can normally be
driven by the CPU or a device providing input to the CPU, even if
some of the row conductors 1 to 8 are shorted together, because a
plurality of keys are simultaneously depressed.   When any of the
address lines A8 to A15 goes low, it will tend to pull a data line
low if any key is depressed.   However, the relatively long time
constant established by the resistors 33 will prevent any
significant change in the voltage on the data line taking place over
the time of a few clock cycles.  Sensing the keyboard requires an
interval of around three times the said time constant in order to
pull the data line reliably low.  This is effected by establishing
the required state of the address lines A8 to A15 and then stopping
the CPU clock for a few tens of cycles, around 2Ous.  The keyboard
settling time is determined by a monostable in the logic array,
similarly to what is described above in relation to Fig. 2.  At the
end of the settling interval, the clock is restarted and the CPU
tests the data bus to ascertain which key was pressed.

     When it is desired to wait for a key to be pressed, a software
routine may be employed, in which all the address lines A8 to
A15 are driven low.

     The following routine will loop until any key is pressed.

START   LD     C,KEYPORT        ; I/O address of the keyboard port
        LD     B,OO             ; Column data zero
LOOP    IN     A,(C)            ; Read the keyboard
        CP     $FF              ; Test for any rows low
        JP     Z,LOOP           ; No keys pressed

     The clock is stopped during the instruction IN A,(C) in order
to freeze the address bus for the requisite number of cycles.  In
order to read which key has been pressed, on exit from the loop, it
is necessary to read the keyboard using the instructions

     LD        B, 11111110
     LD        B, 11111101
     LD        B, 11111011 etc.

     Another way to wait for a keypress is to stop the CPU clock
indefinitely, with all zeroes on the address lines A8 to A15 and
use an eight input NAND gate 34 to provide a signal ANYKEY to the
logic array 11 in order to restart the CPU and perform whatever
routine is appropriate, such as keyboard sensing to determine
which key has been pressed.

     It will be appreciated that the CPU clock must be stopped and
started at appropriate points in the clock cycle.  In practice it
may be stopped halfway through a cycle and restarted at the
beginning of another cycle.

CLAIMS:

1.   A digital computer according to the invention comprising a CPU
(10), RAM (17), ROM (16) and an assemblage of logic (11) providing
ports for a plurality of peripheral devices (12, 13, 14, 18, 19,
20), characterised in that the logic (11) is arranged, in serving at
least one peripheral device (12), to stop the CPU clock for an
interval sufficient to allow settled drive or sense conditions for
that peripheral device to be established.

2.   A digital computer according to claim 1, characterized in that
the CPU (10) is a CMOS CPU.

3.   A digital computer according to claim 1 or 2, characterized in
that the said one peripheral device is a keyboard (12) comprising a
keyboard matrix (A-H, 1-8) connected directly across ports (D0 - D7
and A8 - A15) of the CPU (10) but with the interposition of buffer
resistors (33).

4.   A digital computer according to claim 3, characterized in that
when the CPU (10) is performing a key-scan routine, the clock is
stopped long enough each time before a keyboard output line (A8 -
A15 is sensed for its level to settle high or low, depending upon
whether a corresponding key-switch is closed or not.

5.   A digital computer according to claim 3 or 4, characterized in
that the said resistors (33) are in matrix input lines (D0 - D7)
which are further connected to a fixed potential via pull-up
resistors (32).

6.   A digital computer according to claim 5, characterized in that
the matrix input lines (D0 - D7) are lines of the CPU data bus, and
the matrix output lines (A8 - A15) are lines of the CPU address bus
and include diodes (30) and resistors (31) permitting the CPU (10)
to drive addresses on the address bus.

7.   A digital computer according to any preceding claim,
characterized in that the Cpu (10) and logic (11) are enabled to act
as an EPROM programmer by writing to an EPROM (20) in normal address
space but using lengthened write pulses achieved by stopping the CPU
clock.

8.   A digital computer according to claim 7, characterized in that
the logic (11) comprises a latch (26) which, when set, stops the CPU
clock, and delay means (23, 24, 25) operative when the latch is set
to apply a programming voltage to the EPROM (20) for a preset time
and subsequently to reset the latch (26).

9.   A digital computer according to claim 8, characterized in that
the delay means (23, 24, 25) include a programmable delay stage (24)
for establishing the preset time under program control.

10.  A digital computer according to any preceding claim,
characterized by a continuously running clock oscillator providing
clock signals to the logic (11) and CPU (10) and by means (28) for
preventing the CPU clock signal (PHI) reading the CPU.

Back to Cambridge Computer Limited's Patents